1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly to a shift register circuit for use as a scanning line driving circuit in an image display apparatus or the like and constituted by only field-effect transistors of the same conductivity type.
2. Description of the Background Art
In an image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display, a plurality of pixels are arranged in a matrix in a display panel and a gate line (scanning line) is provided for each row of pixels (pixel line) of the display panel. In a cycle of one horizontal period of a display signal, the gate lines are sequentially selected and driven to update a display image. As a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a multi-stage shift register may be used, which performs a round of shift operation in one frame period of a display signal.
In order to reduce the number of steps in the manufacturing process of a display apparatus, a shift register for use as a gate line driving circuit should preferably be constituted by only field-effect transistors of the same conductivity type. Therefore, various types of shift registers constituted by only N- or P-type field-effect transistors, and various display apparatus containing such shift registers have been proposed (e.g., in Japanese Patent Application Laid-open Nos. 8-87897, 10-500243, 2001-52494, and 2002-133890). As a field-effect transistor, a MOS (Metal Oxide Semiconductor) transistor, a thin film transistor (TFT) or the like is used.
A multi-stage shift register for use as a gate line driving circuit is constituted by a plurality of cascade-connected shift register circuits, each of which is provided for each pixel line, i.e., each gate line. In this specification, for convenience of description, each of a plurality of shift register circuits forming a gate line driving circuit (a multi-stage shift register) is referred to as a “unit shift register.”
As shown in Japanese Patent Application Laid-open Nos. 8-87897, 10-500243, 2001-52494, and 2002-133890 (and FIG. 3 of this specification), a conventional unit shift register includes a transistor (hereinafter referred to as an “output pull-up transistor”) (e.g., a transistor Q1 in FIG. 3) connected between a clock terminal and an output terminal. The unit shift register outputs (activates) an output signal when the output pull-up transistor is turned on and a clock signal inputted to the clock terminal is transmitted to the output terminal.
Hence, in order to speed up the operation of a unit shift register, the rising and falling speeds of the output signal (the speed of the level transitions) need to be increased. For this to be achieved, the output pull-up transistor should have a high drive capability (a capability to pass current) during signal output. One method for this is to increase the channel width of the output pull-up transistor, which however involves the problem of increased area of the circuit.
Another method for improving the drive capability of the output pull-up transistor is to maintain a high gate-source voltage of the output pull-up transistor even during signal output. Since the source of the output pull-up transistor is connected to an output terminal, the source potential increases at the time of signal output; however, at the same time, the gate potential also increases due to capacitive coupling through a gate-channel capacitance, so that the gate-source voltage during that time remains almost unchanged. That is, in order to maintain a high gate-source voltage of the output pull-up transistor during signal output, it is necessary to increase the gate potential of the output pull-up transistor to a sufficiently high level before signal output (before input of a clock signal). For this, precharging the gate electrode at high speed is effective.
In a unit shift register shown in Japanese Patent Application Laid-open Nos. 8-87897, 10-500243, 2001-52494, and 2002-133890, the gate electrode of the output pull-up transistor is connected to a diode-connected transistor (hereinafter referred to as a “charger transistor”). The gate electrode of the output pull-up transistor is charged with supply of an output signal of a unit shift register of the preceding stage through the charger transistor.
However, in a shift register when used as a gate line driving circuit, output terminals of unit shift registers are connected to gate lines which can be large capacitive loads, so that the rising speeds of the output signals become slow. This slows down the speed of charging of the gate electrode of the output pull-up transistor in each unit shift register, resulting in difficulty in speeding up the operation of each unit shift register and thus difficulty in speeding up the operation of the gate line driving circuit.
The charger transistor operates in a source-follower mode during charge of the gate electrode of the output pull-up transistor. That is, as charging proceeds, the gate-source voltage of the charger transistor decreases and the speed of charging slows down with decreasing drive capability. Especially when the rising speed of the output signal of each unit shift register slows down due to the influence of a large capacitive load such as a gate line, the slowdown of the charging speed becomes remarkable because the charger transistor operates in the source-follower mode from the early stage of the charging process. This also becomes a preventing factor of speeding up the operation of the gate line driving circuit.